Shared-memory bank conflicts

For the stated model, successive 32-bit words map to successive banks, wrapping after bank 31. Threads accessing distinct words in distinct banks can be serviced without a bank conflict for that request. Distinct addresses that map to the same bank can require multiple conflict-free operations. A row-major tile’s leading dimension therefore matters: reading a column can produce a very different bank pattern from reading its row, even though both use a two-dimensional array in source code.

Several lanes reading the same shared-memory location are a broadcast case, not a set of distinct-word bank conflicts. Do not diagnose it merely by counting how many lanes map to bank zero. Multiple writes to one location are also a correctness question; a convenient bank pattern does not make conflicting non-atomic writes a defined reduction. Distinguish the requested word addresses, the bank mapping, and the synchronization needed between producers and consumers before changing the layout.

A 32-by-32 row-major FP32 tile has a 32-word row stride. If lane ℓ reads row ℓ at one fixed column, all word indices have the same residue modulo 32 despite being different addresses. Padding the leading dimension to 33 words changes the residue progression so consecutive lanes reach consecutive banks. The extra column is storage overhead used to improve this access pattern; the logical tile can still contain only the original data elements.

Padding is not universally best. It consumes shared memory and may change occupancy, indexing, and copy behavior. Hopper’s TMA supports specific swizzle layouts, documented separately in CUDA 12.8.1, that also require correct producer and consumer indexing. A swizzle is not permission to reinterpret the same bytes with an incompatible row-major formula. Check both the global load pattern and the shared consumer pattern, because fixing one can worsen the other. Preserve numerical element identity through the transformation.

Inspect generated instructions and profiler bank-conflict metrics on the exact target before treating source-level stride arithmetic as a complete performance prediction. Different access widths and compiler transformations matter. Also test producer-consumer ordering: a conflict-free read before the corresponding write completes still reads invalid data. Appropriate warp or block synchronization depends on which threads communicate; do not add a block-wide barrier inside a branch reached by only some required participants. Correctness and layout optimization must be checked together.

The modular lab uses a deliberately smaller eight-residue analogy. Reset, set modulus to 8 and additive step to 4, predict the orbit period, then Step twice. Compare a fresh Reset with both modulus at 8 and additive step at 1, predicting before eight Steps. This shows how a stride changes visited residues. It is not the real 32-bank mapping, and it has no word addresses, broadcasts, memory instructions, or synchronization. Use the separate equation to analyze the actual tile.