Memory interference: capacity limits leave shared traffic

A cgroup memory limit constrains accounted memory usage under its hierarchy; it does not directly cap how often the same cache lines are read or written. A small buffer can generate sustained traffic through repeated streaming, and a large mostly idle mapping can generate little traffic. For an inference worker, model weights, key-value cache, and preprocessing buffers have different access patterns. Record data movement and useful work over the same interval rather than infer bandwidth demand from the resident-set graph alone.

NUMA placement and shared last-level cache determine which tenants compete along a path. A remote memory access may stress a different interconnect from a local access, while shared pages and coherence traffic complicate simple byte counters. Monitoring domains also matter: per-socket or per-cache occupancy is not automatically per-request attribution. Establish counter scope, counter update behavior, sampling interval, and workload placement before comparing measurements. A process migration or page-placement change can alter the observed domain without any change to the tenant’s nominal memory limit.

On supported x86 systems, resctrl cache allocation technology controls eligible cache allocation ways using resource-domain masks. Ordinary shareable groups can have overlapping masks. Exclusive configurations require compatible masks and coordination with the other relevant groups; labeling one group exclusive is not a general proof that all physical interference vanished. Changes govern allocation behavior and do not instantly erase every line a workload previously occupied. Distinguish a mask policy from an observation of current cache contents, and verify what the platform exposes before assuming the feature exists.

Memory bandwidth allocation uses hardware-dependent control semantics; a requested percentage need not translate linearly into an exact number of gigabytes per second. Software feedback modes and the resource domain add their own assumptions. Measure the resulting victim performance and traffic instead of converting a setting directly into a service guarantee. Cache partitioning can reduce a particular eviction interaction while leaving memory buses, shared engines, power effects, or other observation channels shared. Its performance benefit and confidentiality scope therefore require different validation arguments.

For a controlled victim, vary one aggressor mechanism at a time: cache-capacity pressure, a streaming bandwidth load, or a coherence-heavy pattern. Measure useful throughput, tail latency, traffic counters, and allocation settings with warmup and repeatable placement. A cache miss is not a fixed-duration event independent of surrounding traffic, so multiplying all misses by one constant can obscure queueing at the memory controller. Preserve both the trace-level explanation and the physical measurements; each rules out different mistaken explanations for the same application slowdown.

Reset the cache lab, explicitly set capacity two and stride four, predict the result after exactly one Step, then Step once. That produces 17 references at t=0.5 and no hits. For a separate comparison Reset, explicitly set capacity four and stride four, predict, and Step once: four cold misses are followed by 13 hits. This empty, fully associative LRU cache has a four-address cycle. It has no second tenant, real replacement policy, NUMA topology, coherence, or CAT masks, so its result teaches reuse rather than certifying hardware partitioning.