Tensor Core operands: a matrix instruction still needs a layout contract

In a row-major matrix, the leading dimension gives the element distance between successive rows; in a column-major matrix it gives the distance between successive columns. Padding can make that distance larger than the visible row or column length. Declaring the wrong layout can compute a different product even when every access remains inside an allocation. CUDA 12.8's WMMA interface specifies supported shape/type combinations, pointer alignment, leading-dimension constraints, and uniform arguments. These requirements describe that interface rather than every matrix instruction on every accelerator.

A WMMA fragment distributes a matrix tile across a cooperating NVIDIA warp, and the documented element-to-lane mapping is not a portable row-major array layout. Do not infer that one fragment index always names a particular global matrix coordinate across architectures or compilation targets. The collective calls require appropriate participation by all warp threads and uniform control flow under the documented contract. Later architectures also expose different asynchronous or warp-group mechanisms. A working warp-level example is not proof that the same synchronization and fragment assumptions apply to all those paths.

Consider a supported NVIDIA mixed-precision path with FP16 multiplicands and FP32 accumulation. Conversion to FP16 changes the values entering multiplication; FP32 accumulation then operates on those represented inputs under its instruction semantics. Converting the final result back to FP16 adds another rounding stage. FP16 and BF16 both use sixteen storage bits but allocate exponent and significand bits differently, so they are not interchangeable error models. TF32 and other modes have their own contracts. Record the actual library or compiler settings instead of assuming a float32 tensor necessarily implies full-precision scalar multiplication.

A useful reference comparison first separates error relative to the original real-valued problem from error relative to the quantized-input problem. A wider accumulator can improve the latter without fixing the former. Overflow, underflow, cancellation, reduction order, and output conversion remain relevant. Specialized matrix instructions can also have documented accumulation details that differ from a sequential scalar reference. Validate the intended accuracy against representative and difficult inputs, and do not require bitwise equality unless the operation and execution contract actually promises it.

Check device capability, selected kernel implementation, supported element combinations, dimensions, alignment, and tail handling. A compiler or library can choose a fallback when a specialized path is unavailable, so dtype and source-level intent do not prove instruction selection. Inspect the generated path or relevant profiler evidence. Benchmark against a library configured for the same precision policy, including any input conversion and layout transformation that production needs. A fast inner multiply can lose end-to-end if its preparation or output handling dominates.

The matrix lab illustrates conditioning without simulating matrix hardware. Reset, set a=1 and shear b=0, predict singular values one and one and condition number one, then Play or Step. Separately Reset, set a=0.25 and b=0, predict singular values one and 0.25 and condition number four, then Play or Step. The readouts always describe the selected final triangular matrix, while playback interpolates geometry. It does not quantize operands or represent WMMA fragments. Use the changing sensitivity as a reason to test precision choices on more than one convenient input family.