Engineering / advanced
Caches under contention and failure
Design cache keys, eviction, invalidation, stampede controls, and coherence around measurable freshness and resource budgets.
Your route through engineering
Follow the path or begin with a question. Every lesson is open.
Your place, at your pace. Progress is optional and saved only in this browser when available.
Read / explore / reason
Inside this module
Module 01 advanced
Caches under contention and failure
Design cache keys, eviction, invalidation, stampede controls, and coherence around measurable freshness and resource budgets.
- 01
Cache keys are equivalence claims
Design canonical keys that preserve tenant, authorization, representation, and source-version boundaries.
24 min - 02
Admission is not eviction
Separate deciding what enters a cache from deciding what leaves under memory pressure.
24 min - 03
Reuse distance and an LRU miss curve
Connect distinct intervening keys to a precise fully associative LRU condition without generalizing it to every cache.
24 min - 04
TTL jitter and explicit stale windows
Spread expiration work without silently extending the maximum freshness contract.
24 min - 05
Coalescing misses without stale leaders
Bound duplicate origin work while preserving waiter deadlines and rejecting outdated refresh results.
26 min - 06
Write paths and cache-aside races
Specify acknowledgment and recovery semantics before comparing write-through, write-back, and cache-aside patterns.
26 min - 07
Consistent hashing and a membership change
Quantify expected key movement under explicit placement assumptions without confusing balance, hotness, or replication.
25 min - 08
Negative caching without inventing absence
Cache well-scoped absence separately from permission failures and transient errors, with bounded recovery delay.
24 min - 09
Invalidation with versions and retained guards
Reason about duplicate, reordered, delayed, and missing events without turning best-effort notifications into a consistency proof.
27 min - 10
Observe cache value and test safe bypass
Connect useful reuse, freshness, and origin headroom instead of treating hit ratio as the cache's complete health signal.
26 min