advanced24 min studyLesson 323 in Engineering

Reuse distance and an LRU miss curve

Connect distinct intervening keys to a precise fully associative LRU condition without generalizing it to every cache.

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What you’ll understand

  • Compute reuse distance as distinct intervening keys.
  • Apply the correct strict inequality for a count-bounded LRU hit.
  • Explain how sizes, expiration, and admission change the model.

The number of requests since the last access is not the same as reuse distance. Ten repeated requests to one other key consume only one distinct position in an ideal LRU stack. Counting distinct intervening keys lets us predict hits for a narrowly defined cache and build a capacity-versus-miss curve. State that model carefully before carrying its conclusions into a production service with variable objects, expiry, and concurrency.

Distance is counted in distinct competitors

For a repeated reference to key x, count the distinct other keys accessed since the previous x. That is the reuse distance under the convention used here. A first reference has no previous occurrence and is cold. In a fully associative C-entry LRU cache that admits all misses, stores equal-size entries, and has no expiration or external invalidation, x hits exactly when this distance is less than C. Equality means enough distinct competitors have displaced it.

Consider A, B, B, C, A. Between the two A references are three requests but only two distinct keys, B and C. A three-entry LRU cache can retain A through those competitors, while a two-entry one cannot. Write the actual recency list after each operation if the boundary feels confusing. Hit accesses update recency too; ignoring them changes the policy being simulated and can produce an incorrect trace even when the resident key set initially looks plausible.

hit⁡(x;C)  ⟺  d(x)<C\operatorname{hit}(x;C)\iff d(x)<C
d is the number of distinct other keys since the previous x, with cold references excluded from finite distances. C is a positive entry count. The equivalence requires the stated fully associative equal-size admit-all LRU model with no expiry or invalidation.↔ Scroll wide equations horizontally.

A trace produces a model-specific miss curve

Count cold references separately and group repeated references by reuse distance. For each candidate capacity, add cold references and repeated references whose distance is at least that capacity. Dividing by all references gives the miss ratio for this trace under the specified LRU model. It is a historical calculation, not a guarantee that the future workload has the same distribution. Warm-start state and trace truncation can change which references are classified as cold.

Byte-bounded caches require object-size-aware reasoning, and TTL or invalidation can remove an entry even when its stack distance is small. Admission rejection also breaks the admit-all premise. Distributed caches add placement and independent per-node budgets; a global trace curve cannot automatically predict each shard's pressure. Treat the simple curve as a baseline hypothesis and explain every extra mechanism before comparing it with a measured application hit ratio.

M(C)=Ncold+∑d≥CNdNtotalM(C)=\frac{N_{\rm cold}+\sum_{d\geq C}N_d}{N_{\rm total}}
Nd counts repeated references with finite reuse distance d. All N quantities count requests within one declared trace and initial-state convention. M is dimensionless and applies to the specified LRU model only.↔ Scroll wide equations horizontally.

Inspect a cyclic working set

A deterministic cyclic workload makes the capacity boundary easy to verify. If the cycle has P distinct keys and no other requests intervene, each repeated reference has distance P−1. A capacity of at least P retains the cycle after cold fills; smaller capacity misses continually under admit-all LRU. This is not a claim that real traffic is cyclic. It is a useful diagnostic example for learning why a one-entry capacity difference can change reuse sharply.

Reset the cache lab and set both C=4, s=4. Its (i×s) mod 16 stream has period four; predict four misses and twelve hits among its initial sixteen requests, then Step to add one hit. For a separate run Reset and re-set C=3, s=4; predict sixteen misses. The trace starts empty and caps at 4096 requests. These are abstract equal-size entries with no TTL or admission filter, so this activity directly tests the stated LRU distance condition rather than a Redis implementation.

A five-request trace

Run the cold trace A, B, B, C, A with admit-all fully associative LRU. Compare capacities two and three, treating all keys as equal size.

  1. A and the first B are cold misses. The second B hits. C is a cold miss, and the final A has reuse distance two because B and C are the distinct intervening keys.

  2. At capacity two, distance two is not less than capacity, so final A misses. There are four misses and one hit, giving a 20% hit ratio.

  3. At capacity three, final A hits. There are three cold misses and two hits, giving a 40% hit ratio. Repeated B requests do not increase A's distance beyond the distinct-key count.

The result

The strict distance-versus-capacity boundary predicts the trace without confusing repeated requests with distinct competitors.

Explore the model

Interactive lab

Interactive lab · cache

The strict LRU capacity boundary

Reset, set C=4, s=4; predict 12 hits in 16 requests and another hit on Step. Reset and re-set C=3, s=4; predict zero hits. The fully associative equal-entry LRU trace starts empty and caps at 4096; it has no expiry, invalidation, or admission filtering.

The strict LRU capacity boundaryA fully associative LRU cache starts empty and requests address (i·s) mod 16. Hits move an address to the newest position; misses evict the oldest when full. Playback starts with 16 requests and adds two per second, capped at 4096 explicitly simulated requests. This toy stream is not a processor-cache benchmark. Current readings: Hits / requests: 0 / 16; Hit rate: 0%; Address-stream period: 16 addresses. All parameters are adjustable with the labeled controls below.Fully associative LRU cache after 16 deterministic requests: 0 hits and 16 misses.Most recent 16 requestsaddress = i × 3 mod 160M3M6M9M12M15M2M5M8M11M14M1M4M7M10M13MCurrent cache order · oldest → newest471013Latest address 13 · miss: inserted as newestToy address stream · period 16 · starts empty
Cached addressMiss / evictionMost recent request
Hits / requests
0 / 16
Hit rate
0%
Address-stream period
16 addresses
t = 0 s

A fully associative LRU cache starts empty and requests address (i·s) mod 16. Hits move an address to the newest position; misses evict the oldest when full. Playback starts with 16 requests and adds two per second, capped at 4096 explicitly simulated requests. This toy stream is not a processor-cache benchmark. Parameter changes pause playback and recompute the model at the current elapsed time. Reset restores both parameters and returns time to zero. Playback starts paused. Adjust either parameter, then choose Play or Step.

Look forA period-four cycle has reuse distance three, so C=4 hits after warmup while C=3 does not.

Check your understanding

A repeated key has reuse distance four under the stated LRU convention. What happens in a four-entry admit-all cache with no other removal mechanism?

Try it yourself

For cold trace A, B, C, B, A, D, A, compute the final A's reuse distance and decide whether that final access hits in capacity two. Do not assume the earlier A access hit.

Take a moment to make a prediction or work it out on paper. Open a hint when you need one.

Give me a hint

Only references after the immediately preceding A contribute to the final A's distance.

Compare with the solution

The immediately preceding A is the fifth reference. Only D appears between it and the final A, so distance is one and the final A hits in capacity two. The fifth A itself has distance two, from distinct B and C, and misses at that capacity. Every access, including a miss that is admitted, establishes a new recency position for subsequent references.

Take it with you

  • Reuse distance counts distinct intervening keys.
  • The equal-entry LRU hit condition is d<C, not d≤C.
  • Miss curves inherit initial-state, admission, size, and expiration assumptions.

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