TLBs and the working set of translations

A TLB hit supplies a cached translation and relevant permission information for the access. A miss can trigger a hardware page-table walk, or an architecture-specific software mechanism, to recover the mapping. Page-table entries themselves are stored in memory and may benefit from caches and dedicated walk caches. The translation machinery therefore has its own access pattern and overlap limits. Counting one miss as one fixed-cost main-memory access is usually too crude for a real performance model.

A page fault is a different condition requiring operating-system handling, such as an absent mapping, a protection violation, or deferred population of a valid region. A resident, permitted page may require a TLB refill without any page fault. Conversely, a fault may involve allocation, copy-on-write, or I/O and cost far more than an ordinary walk. Name the event precisely and inspect the architecture and operating-system definitions before converting a counter into a latency estimate.

Touching a few bytes on many pages can exhaust translation entries while consuming little useful payload. Repeatedly processing all nearby elements within a page may amortize translation work, provided the access order is legal. Just as cache associativity can matter before byte capacity is exhausted, TLB set conflicts may matter before nominal reach is exhausted. A reach calculation is a useful scale estimate; it does not prove that every mapping within that byte span stays cached.

Larger pages can increase bytes covered per translation, but their allocation and management costs differ. They can increase internal fragmentation, complicate placement, or require expensive promotion and compaction. Support and available TLB capacity may differ by page size, so multiplying an unchanged entry count by a larger page size is only a hypothetical comparison unless hardware documentation justifies it. Measure the full workload and memory pressure rather than treating huge pages as a universal optimization.

When software changes a mapping or permission, cached translations must cease supplying an obsolete interpretation where required by the architecture. Operating systems use invalidation mechanisms and coordinate with processors that may retain relevant entries. This can create cross-core work, often called a TLB shootdown. Precise invalidation can preserve unrelated translations, while broader invalidation may be cheaper to issue but cause extra refills. The tradeoff depends on the architecture, affected range, and active processors.

The function lab shows y=ax² and nothing about translation. Interpret positive x as a normalized side length of a dense square allocation and positive a as bytes per entry, then predict its growth. Use that payload to motivate a separate page-count calculation under a declared page size. The sliders cannot select page size, TLB entries, or invalidation scope. This separation matters: a smooth payload curve does not imply a smooth transition in discrete page counts or measured walk costs.