Engineering / core
The memory hierarchy in practice
Explain locality, coherence, translation, and bandwidth limits before interpreting measurements from real processors.
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Module 01 core
The memory hierarchy in practice
Explain locality, coherence, translation, and bandwidth limits before interpreting measurements from real processors.
- 01
Cache lines and useful locality
Count the bytes a program consumes and distinguish reuse from merely adjacent addresses.
21 min - 02
Cache mapping, associativity, and conflicts
Trace an explicit set-associative example and separate capacity pressure from mapping conflicts.
22 min - 03
Coherence and permission to write
Reason about shared copies, ownership transitions, and the boundary between coherence and synchronization.
24 min - 04
Memory consistency and observable order
Use small execution arguments to distinguish per-location coherence from ordering across multiple addresses.
25 min - 05
False sharing and ownership-aware layout
Identify independent fields that interfere through shared cache-line ownership, then evaluate padding as a measured tradeoff.
22 min - 06
Prefetching, timeliness, and wasted work
Reason about bringing data early without confusing hidden latency with reduced traffic.
23 min - 07
NUMA placement and remote memory
Connect thread placement, page allocation, and communication patterns without treating locality as a universal speed guarantee.
24 min - 08
TLBs and the working set of translations
Separate address translation misses from data misses and page faults, then reason about page-size tradeoffs.
24 min - 09
Roofline bounds and the traffic boundary
Use operational intensity to reason about compute and bandwidth ceilings while separating an upper bound from a throughput prediction.
26 min - 10
Hardware counters as evidence
Turn event counts into defensible ratios while checking scope, multiplexing, and competing explanations.
25 min