Coherence and permission to write

In the simplified MESI vocabulary, Invalid means a cache lacks a usable copy, Shared permits reading a potentially shared clean copy, Exclusive denotes a clean private copy, and Modified denotes the private dirty owner. Clean and dirty compare the cached contents with backing memory at the relevant point in the protocol. Other protocols add states or use different names. A real implementation also needs transient states while messages, acknowledgments, and data are in flight.

The useful invariant is that write permission excludes other valid readable copies until the protocol completes the necessary transition. Multiple readers can coexist when no writer has exclusive permission. A reader requesting data currently held dirty elsewhere may receive the up-to-date data through the coherence fabric rather than through an immediate memory writeback. Those choices change traffic and latency, but the hardware must still satisfy its specified coherence and memory-model rules.

Suppose two workers each load zero, compute one, and store one to the same counter. The final value can be one even if the underlying reads and writes participate in a perfectly coherent system. The problem is that the entire read-compute-write sequence was not one atomic operation. Ownership can pass between stores after both workers have already calculated their private results. Coherence cannot reconstruct the increment that the program failed to make indivisible.

In a language such as C++, unsynchronized conflicting accesses to an ordinary shared object can additionally create a data race with undefined behavior. Use the language's atomics or synchronization primitives rather than translating this explanatory hardware trace into unsafe source code. Atomic fetch-add can make each increment indivisible, while its chosen memory order controls additional ordering guarantees. Coherence, atomicity, language legality, and inter-address ordering are related layers with different responsibilities.

A line repeatedly modified by different cores may require repeated permission transfers and data movement. Keeping most updates within one owner and combining them less frequently can reduce that traffic, but only if the algorithm permits delayed aggregation. A hot lock and its protected data may create a different access pattern from a read-mostly configuration object. Identify actual writers and readers, their placement, and how often ownership must change before proposing a new layout.

The reliability lab displays replica count n, unavailable count k, and majority threshold floor(n/2)+1. Increase k and predict when a majority disappears. This is explicitly a contrast: its circles are not CPU cache copies and its threshold does not implement MESI. A count of available copies says nothing about write permissions, message ordering, or the value a load may observe. Explain which missing state and transition rules a genuine coherence visualization would need.