Memory consistency and observable order

For sequential consistency, the observed results must be explainable by one total order of the operations that preserves each participating thread's program order. The machine need not literally execute every instruction serially. It may overlap and speculate internally so long as the visible result meets the contract. Initial values can be treated as preceding the tested operations. A proof therefore looks for a compatible ordering rather than guessing a processor's exact internal timing.

Weaker architectural models preserve selected dependencies and ordering constraints while permitting other outcomes. That flexibility can support implementation techniques such as buffering stores or overlapping memory requests. It does not mean all reorderings are allowed. The RISC-V RVWMO specification, for example, defines precise constraints and explicit ordering mechanisms. Check the relevant instruction types, dependencies, memory attributes, and fences; a slogan such as 'weak architecture' is not a complete execution model.

Let x and y start at zero. Thread A stores one to x and then loads y; thread B stores one to y and then loads x. Under sequential consistency, both loads cannot return zero. Each zero observation would place its load before the other thread's store, while program order places each thread's own store before its load. Combining those requirements forms a cycle, contradicting a single total order.

Some weaker hardware models permit the both-zero observation for suitable ordinary memory operations. A store can remain buffered while a later load of another location proceeds, provided the architecture's rules allow it. This is not evidence that coherence failed for x or y. At source level, use a legal litmus test with appropriately chosen atomic operations or an architecture-specific harness. Ordinary racy C++ variables cannot be justified by a hardware-level argument about possible reordering.

A producer often writes a payload and then signals readiness. A consumer that observes readiness needs a documented guarantee before reading the payload. In suitable source-level code, a release operation and an acquire operation that synchronizes with it can establish the required happens-before relationship. A relaxed atomic flag is not a universal publication mechanism. Likewise, adding a hardware fence in one place does not automatically repair arbitrary source-language races or every surrounding algorithm.

The waves lab combines two fixed-frequency sine waves with phase difference and amplitude ratio controls. Set equal amplitudes and predict cancellation near a 180-degree phase difference. Use this only to contrast a continuous phase variable with a logical ordering relation: memory order is not a wave phase, and changing the slider cannot test a litmus program. After inspecting the cancellation, return to the four-operation cycle and identify which ordering edges a real synchronization design must establish.