Loads, stores, and the address calculation

In a byte-addressed system, adjacent address numbers identify adjacent bytes. A packed array of four-byte elements therefore advances its element address by four, not one. RV32I loads and stores form an effective address by adding a sign-extended 12-bit immediate to a base register. An array index larger than that immediate range may require separate arithmetic. The effective address is an address-sized bit pattern; whether an application owns the corresponding memory is a different question.

Endianness describes how a multibyte value is arranged across addressed bytes. In a little-endian environment, the least significant byte occupies the lowest address. For bytes 0x78, 0x56, 0x34, 0x12 at increasing addresses, a four-byte integer load yields 0x12345678. State the environment because RISC-V permits execution environments to define endianness. Reinterpreting a network packet by blindly loading a host integer can reverse the intended significance, and unaligned or forbidden accesses introduce additional concerns.

An RV32I LB reads one byte and sign-extends its eight-bit value to 32 bits; LBU reads one byte and zero-extends it. If that byte is 0xFE, LB produces 0xFFFFFFFE, interpreted as minus two when signed, while LBU produces 254. Both read the same memory byte. The distinction belongs to the load instruction, not to a tag stored alongside that byte. Stores select low-order source bits for the requested width; they do not preserve an abstract high-level type.

Naturally aligned accesses have addresses divisible by their width. The RISC-V execution environment specifies how misaligned loads and stores are handled, including whether support is invisible or an exception occurs. Do not assume a misaligned access is cheap or atomic merely because it works on one machine. Similarly, crossing a page boundary can require access to two mappings. An aligned address calculation avoids one class of problem but does not establish that every accessed byte belongs to the object or is permitted.

Before loading element i of an n-element array, establish that i lies from zero through n minus one, that the address arithmetic has the required language semantics, and that the array is still alive. Memory protection operates at mappings and permissions, so an out-of-bounds access can land inside a mapped page and still violate the program’s contract. A successful load is not proof of bounds safety. Concurrent mutation, device memory, and atomics bring further rules outside this ordinary single-threaded example.

The function lab shows the exact curve y=ax², with its tangent and area. It can illustrate how a quadratic pair table’s payload grows when positive x represents normalized item count and positive a represents normalized bytes per pair entry. Use x=0.5 and then x=1 to predict the fourfold change. It does not display addresses, endian conversion, cache misses, or page faults. Use hand traces for those semantics, then use real tools and the documented memory model when diagnosing an implementation.