Instructions and execution

Connect instruction-set contracts to pipelines, retirement, and the costs that programs expose to hardware.

10 published lessons1 module220 min of guided study
  1. 01
    Instructions and executioncore · 10 lessons

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Instructions and execution

Connect instruction-set contracts to pipelines, retirement, and the costs that programs expose to hardware.

  1. 01

    Instruction sets: the contract beneath a program

    Separate architectural behavior from processor implementation and trace a small RV32I program without assuming its timing.

    22 min
  2. 02

    Arithmetic, flags, and three meanings of overflow

    Calculate fixed-width sums and distinguish unsigned carry, signed overflow, and language-level arithmetic rules.

    22 min
  3. 03

    Loads, stores, and the address calculation

    Trace byte-addressed memory, sign extension, and bounds separately from whether an address can be formed.

    22 min
  4. 04

    Calling conventions: make functions agree

    Trace System V AMD64 argument registers, preserved state, return addresses, and ordinary stack alignment.

    22 min
  5. 05

    Branches: correctness before prediction

    Separate a branch condition from a predictor’s guess and estimate recovery cost without inventing a universal penalty.

    22 min
  6. 06

    Pipelines: overlap work without erasing dependencies

    Derive an ideal pipeline bound, then distinguish data hazards, structural conflicts, and control uncertainty.

    22 min
  7. 07

    Out-of-order execution: readiness before source order

    Trace dependency graphs, register renaming, and finite scheduling windows without confusing completion with commitment.

    22 min
  8. 08

    Precise exceptions: finishing is not committing

    Explain how speculative results can finish early while retirement maintains an ordered architectural boundary.

    22 min
  9. 09

    SIMD: lanes have exact arithmetic semantics

    Trace SSE2 packed integer addition, distinguish wrapping from saturation, and count vector tails honestly.

    22 min
  10. 10

    Microbenchmarks: measure the question you actually asked

    Design controlled latency and throughput experiments while distinguishing core cycles, elapsed time, and timestamp-counter ticks.

    22 min
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