Out-of-order execution: readiness before source order

If instruction B reads the result of instruction A, B cannot compute the correct value before A produces it. This read-after-write edge is a true dependency. An independent instruction C may execute while A waits for a load, provided C is available to the scheduler and its own resources are ready. Draw values as edges and operations as nodes. Source-code line order alone can hide this parallelism, especially after a compiler transforms loops or introduces extra address arithmetic.

A critical path is a chain whose successive dependent latencies cannot overlap with one another. Independent work can fill otherwise unused execution capacity but cannot shorten that chain without changing the computation. If four dependent operations each require three cycles before their outputs can be used, their chain needs at least twelve cycles under that latency assumption. Four independent operations might overlap substantially, but their throughput still depends on available execution resources. State both dependency and capacity assumptions before comparing the two.

Architectural registers are a limited set of visible names. Two instructions that both write a name need not represent the same internal storage location. Register renaming assigns distinct physical destinations to different versions, allowing a later independent write to execute without overwriting a value that an older instruction still needs. This can remove write-after-write and write-after-read name dependencies. It does not remove a read-after-write dependency when a consumer genuinely needs the value produced by a particular instruction.

Imagine an older instruction reading the old value of R1 while a younger independent instruction writes a new R1. Distinct physical versions let both needs coexist. The rename mapping tracks which version each read should use, rather than letting the younger write destroy the older input. Physical registers, scheduling entries, load/store structures, and reorder capacity are finite. A long wait can fill those structures and stop additional useful work from entering, so an unlimited-window schedule is only an upper-bound thought experiment.

Loads and stores need more than register readiness. Their addresses may not yet be known, and a younger load could refer to data written by an older store. Implementations can predict or check dependencies and recover when speculation was wrong, but must satisfy the architecture’s memory rules. This does not grant a language-level data race defined behavior. Likewise, an executed wrong-path operation may have microarchitectural effects even though it never becomes a committed instruction result; architectural recovery is not a claim of side-channel invisibility.

The network lab makes a single computation graph inspectable: a multiply and offset feed a sigmoid. Change x or w, and predict which downstream quantities change. It does not animate instruction scheduling, register renaming, or speculative memory. Its useful lesson is that outputs depend on specific inputs. Draw a separate dependency graph for the worked schedule and ask which missing input blocks a node. That reasoning supports realistic experiments such as using multiple independent accumulators, with care about changed floating-point evaluation order.