Engineering / research
Co-design models and heterogeneous machines
Compare emerging hardware and placement mechanisms through explicit workload models, numerical constraints, and measured evidence rather than assumed universal speedups.
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Module 01 research
Co-design models and heterogeneous machines
Compare emerging hardware and placement mechanisms through explicit workload models, numerical constraints, and measured evidence rather than assumed universal speedups.
- 01
Place a workload graph rather than a peak operation count
Compare heterogeneous placements using dependencies, transfer edges, memory feasibility, and resource contention.
28 min - 02
Overlap work only while its data remains valid
Construct a CPU, transfer, and GPU pipeline with explicit completion events, buffer lifetimes, and measured concurrency.
28 min - 03
Separate coherent access from cheap access
Read CXL device capabilities and region semantics before modeling latency, sharing, synchronization, or offload.
28 min - 04
Buy memory capacity with an explicit access policy
Model local-cache hits, remote-fetch cost, migration amortization, and phase changes in a disaggregated memory tier.
28 min - 05
Budget the pipeline you can actually synthesize
Relate initiation interval, first-result latency, memory traffic, and implemented resource limits in FPGA inference.
28 min - 06
Map local work and global traffic separately
Model mesh cuts, placement, memory residency, and communication collectives on a wafer-scale machine.
28 min - 07
Account for the movement that remains near memory
Compare digital and analog near-memory designs using supported operations, precision, host traffic, and complete energy boundaries.
28 min - 08
Budget the complete optical communication path
Separate one-way payload bandwidth, serialization, conversion, propagation, and energy at the declared accounting boundary.
28 min - 09
Count useful sparse work and the metadata around it
Map nonzeros and events through storage, scheduling, routing, and quality constraints instead of inferring proportional speedup.
28 min - 10
Choose a design point that meets the whole contract
Compare heterogeneous hardware and model changes through matched quality, loaded latency, complete costs, and reproducible evidence.
28 min