Account for the movement that remains near memory

Digital near-memory cores execute an instruction set with finite local storage and memory-transfer rules. Their usefulness depends on native arithmetic, available parallelism, and communication between partitions. The referenced UPMEM training study evaluates specific classical learning algorithms and reports the importance of supported operations and data representations. It is not evidence that arbitrary deep-learning training automatically accelerates. Host-mediated communication or packing can dominate an algorithm whose independent memory-local work is too small.

Analog crossbars instead use physical conductances and electrical signals for parts of a dot-product computation. A complete accelerator needs input encoding, output conversion, signed-value handling, accumulation, and control. The ISAAC design uses bit slicing and supporting digital structures; one array operation should not be described as an arbitrary full-precision multiply-accumulate. Distinguish an analog device operation from a complete numerically specified matrix multiplication, including the passes and conversions required by its representation.

Fixed-point, quantized, bit-serial, and analog implementations must meet the same declared application-quality requirement as their baseline. Include dynamic range, overflow, saturation, accumulation width, conversion precision, and calibration effects. Replacing a nonlinear function with a lookup table changes both implementation and approximation. Validate the complete model’s output or learning behavior rather than checking only one ideal dot product. A nominal precision label does not uniquely identify the numerical error produced by the full execution path.

Separate one-time and repeated costs. Writing or programming weights may be amortized over many inferences but can dominate frequent updates. Packing data into the required memory layout may be cheap once and expensive if repeated for each batch. Include local reads, host reductions, and intermediate writebacks in the movement ledger. A reduction in host-link bytes is a useful mechanism measurement, but it cannot by itself determine end-to-end latency or energy when arithmetic and conversion costs change.

Use a baseline optimized for the same task, precision target, data residency, and batch size. If the near-memory design changes the model to fit its instruction set, report that model-quality change and any retraining cost. Include host CPU work and the memory modules or external devices needed to run the algorithm. A per-array energy figure cannot be compared directly with a wall-plug whole-system inference measurement without reconciling their boundaries.

Evaluate scaling under skew and shared-resource contention. Independent partitions may scale well until a reduction or host path dominates, while an unbalanced partition can leave nearby compute idle despite abundant aggregate bandwidth. Report which algorithms and operators actually run on the memory-side device and which fall back elsewhere. Present the result as a workload-specific design point with an explanation of saved movement and added costs, rather than as a universal consequence of putting computation closer to storage.