Map local work and global traffic separately
Model mesh cuts, placement, memory residency, and communication collectives on a wafer-scale machine.
On this page
The question for today
What you’ll understand
- Compute a directional mesh-cut bandwidth bound.
- Explain why nearest-neighbor bandwidth does not imply cheap all-to-all traffic.
- Distinguish within-wafer placement from external-memory and multi-system costs.
Placing many processing elements and local memories on one wafer changes the cost of fine-grained communication, but it does not erase topology. Neighbor exchanges, reductions, transposes, and all-to-all traffic impose different movement patterns. A workload that fits local memories and communicates mostly with nearby elements can behave very differently from one that repeatedly crosses a narrow global cut. Start with a communication graph and actual placement, then account for directional link capacity, message volume, buffering, and any traffic leaving the wafer. The numerical mesh below is fictional, not a specification of a commercial machine.
Distinguish edge bandwidth from a network cut
A two-dimensional mesh has many short links, but a balanced left-right cut intersects only a column of links. Adding processing elements increases local arithmetic capacity faster than some global communication cuts. For a given placement, count bytes that must cross each relevant cut and compare them with its directional capacity. Opposite directions may use distinct full-duplex resources; do not add both capacities when all required bytes flow one way. Routing and competing traffic can reduce achievable rate below the cut bound.
Nearest-neighbor stencils can reuse local links well, while transposes and broad reductions can move data through many hops. Hop count contributes contention and buffering demand even if each message’s endpoint distance is modest. Treat a communication collective as a scheduled algorithm rather than an abstract operation with zero cost. The wafer-scale FFT and Reduce papers study specific communication structures and implementations; their results should be read with their problem sizes, precision, and machine generation attached.
Place state so the useful work remains local
Local memory capacity determines how much of each tensor shard and its temporary state can remain near computation. Include live inputs, outputs, partial sums, and routing buffers rather than only weights. Overly fine partitioning can reduce per-element storage while increasing halo or reduction traffic. Overly coarse partitioning can exceed local capacity or leave too little parallelism. Search the interaction between shard shape, compute granularity, and communication pattern, then validate the chosen mapping.
Within-wafer bandwidth is not interchangeable with off-wafer ingress, egress, or external weight supply. A model that exceeds local capacity may need another execution strategy, additional storage, or explicit streaming. Include that traffic and its scheduling in end-to-end time. Likewise, scaling across several wafer-scale systems introduces another interconnect tier. A measured local-kernel result does not establish that a large training job, checkpoint, or input pipeline scales at the same rate.
Compare full workloads at matched numerical quality
Explain the numerical representation, accumulation, reduction order, and any precision changes used by the mapping. A high-throughput local operation is meaningful only if the overall algorithm meets the quality or tolerance target. Collective ordering can change floating-point results, so validate more than a single output bit pattern unless bitwise equivalence is actually required. Retain problem size and placement with every timing to prevent favorable small cases from standing in for capacity-limited ones.
Measure strong and weak scaling separately, include external data loading when it is part of the application boundary, and report mapping or compilation costs when they matter operationally. Monitor hot links, local-memory pressure, and idle processing elements to test the cost model’s explanation. Vendor peak arithmetic and aggregate on-wafer link totals describe capability ceilings, while measured workload time depends on how that workload uses them. Neither a large wafer nor many cores supplies a universal advantage for every communication graph.
Work it through
A fictional mesh has a finite directional bisection
Consider an 8×8 mesh with a left-right balanced cut crossing 8 links. Each link carries 10 decimal GB/s in each direction independently. A phase must move 4 decimal GB from the left half to the right half. Compute its ideal cut bound and compare with a 20 ms arithmetic lower bound.
The relevant one-direction cut capacity is 8×10=80 GB/s. The reverse-direction channels do not double capacity for bytes that all travel left to right.
The crossing time is at least 4 GB/(80 GB/s)=0.05 s=50 ms, before startup or contention. This is a topology bound, not a complete routing schedule.
Combining this with the arithmetic lower bound gives total phase time at least max(50,20)=50 ms. Perfectly adding unrelated local links elsewhere in the mesh cannot remove the required cut crossing.
The phase is bounded by global traffic in this synthetic model even though local arithmetic might finish in 20 ms. Attaining 50 ms would still require a valid schedule and no additional bottlenecks.
The living notebook
Explore the model
Interactive lab · modular
A logical communication stride changes the visited set
Reset, set Modulus m to 8 and Additive step a to 1. Predict period 8 and residues 1,2 after two Steps. Reset, explicitly set m=8 and a=2, then take two Steps: predict residues 2,4 and period 4. This exact additive orbit illustrates logical index visitation only; it has no mesh links, routing, byte volume, or wafer-scale timing.
- Residue r0
- 0
- Orbit period · m/gcd(m,a)
- 12
- Distinct residues visited
- 1 of 12
Addition modulo m starts at zero: rₙ = na mod m. Playback advances two additions per second. The orbit has period m/gcd(m,a), including period one for a = 0. This is not a cryptographic security test or a primality algorithm. Parameter changes pause playback and recompute the model at the current elapsed time. Reset restores both parameters and returns time to zero. Playback starts paused. Adjust either parameter, then choose Play or Step.
Look forA logical access pattern must be mapped to the physical topology before costs are assigned.
Pause & reason
Check your understanding
Your turn
Try it yourself
A fictional 16×16 mesh cut crosses 16 links, each providing 5 decimal GB/s in the needed direction. A phase must send 8 GB across it and has an arithmetic lower bound of 60 ms. Find the cut and combined lower bounds.
Take a moment to make a prediction or work it out on paper. Open a hint when you need one.
Give me a hint
Aggregate only directed links that cross the cut, then take the maximum of necessary resource times.
Compare with the solution
Cut capacity is 16×5=80 GB/s, so the required transfer takes at least 8/80=0.1 s=100 ms. The combined lower bound is max(100,60)=100 ms. It does not prove a 100 ms implementation because routing, dependencies, external movement, and contention may add cost.
Keep the idea
Take it with you
- Use directional cuts and actual placements to model global traffic.
- Account for local-memory residency and off-wafer movement separately.
- Compare matched numerical workloads, not aggregate capability totals.
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